例句與造句

1. circuit level gateway
   電路層網(wǎng)關器
2. computer architecture, barcelona, spain, june 27-july 1, 1998, pp . 282-292.6 buyuktosunoglu a et al . a circuit level implementation of an adaptive issue queue for power-aware microprocessors
   2對位于第二級的發(fā)射隊列利用寄存器標簽進行多體劃分，更進一步減小發(fā)射隊列的大小和比較器的位寬。
3. the proposed 64 bits high performance alu is optimized at algorithm level, logic level, circuit level and layout level, and is implemented in 0.18 m cmos process . furthermore, the testing technique of the alu is discussed . this thesis mainly contributes to the following aspect : 1
   文章從部件的算法、邏輯結(jié)構、電路參數(shù)、物理版圖等多個層次進行設計優(yōu)化,在0.18mcmos工藝下實現(xiàn)了一款64位高性能算術邏輯部件,并對該部件的測試方法進行研究。
4. therefore, they serve as restricts to design these blocks at the circuit level . secondly, based on the study of the resistor offset averaging network, a capacitance offset averaging network is designed . the differential non-linearity ( dnl ) and the integral non-linearity ( inl ) are reduced 70 % by applying this capacitance offset averaging network
   其次,研究了電阻誤差平均網(wǎng)絡的特性,設計了電容誤差平均網(wǎng)絡,分析可得此電路技術可改善電路微分非線性(dnl)和積分非線性(inl)達70%以上,和電阻誤差平均網(wǎng)絡對dnl抑制效果好不同,電容誤差平均網(wǎng)絡對inl的抑制程度是對dnl的抑制程度的2倍以上。
5. on the aspect of the dynamic character, the electrocircuit model of the motor is being realized on the pspice environment . the transient character of the pmlsm under the sinusoidal power is reached using the pspice model at circuit level, the results are compared with those using time-stepping fem
   從電機的動態(tài)性能方面：建立了電機的pspice模型，在pspice環(huán)境下對電機進行正弦波驅(qū)動下瞬態(tài)特性的仿真，并與以電磁場分析為基礎的時步有限元電機的動態(tài)仿真分析進行了比較。
6. It's difficult to find circuit level in a sentence. 用circuit level造句挺難的